The electronics industry continues to rely upon advances in semiconductor technology to realize higher-functioning devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
A wide variety of techniques have been used in IC devices to ensure that, once they are manufactured, they operate fully in compliance with their intended design and implementation specifications. Many of the more complex IC designs include circuits that permit in-circuit testing via the IC access pins. The IEEE 1149.1 JTAG recommendation, for example, provides a test circuit architecture for use inside such ICs. This architecture includes a test access port (TAP) controller coupled to the IC pins for providing access to and for controlling various standard features designed into such ICs. Some of these features are internal scan, boundary scan, built-in test and emulation.
The JTAG recommendation was developed with the understanding that such IC designs would be using only one test access port controller. Sometime after its initial development, however, many IC's are being designed with multiple "core" circuits, such as multiple CPUs, with each core circuit including its own TAP controller. Typically, separate IC pins are used to select one of the TAP controllers for testing and/or debugging the IC. This is problematic, however, in IC applications that require an increasing number of core circuits without increasing the circuit area of the IC and/or the number of IC pins.
One approach that attempts to overcome such difficulty involves use of an internally implemented circuit for selecting which of the TAP controllers is activated during a test/debug mode of operation inside the TAP controller itself. This approach requires a change to the existing structure of the TAP controllers so that special signals can be drawn from and fed to each TAP controller, and requires that each TAP controller have knowledge that it is enabled at a given time. For many applications, however, changing the design of the established TAP controller is expensive. Further, for certain applications, requiring that each TAP controller have knowledge that it is enabled at a given time adversely removes a desired degree of transparency.
For further information concerning with the above issues, reference may be made to an article entitled, "An IEEE 1149.1 Based Test Access Architecture for ICs with Embedded Cores," by Lee Whetsel, and to IEEE Std. 1149.1-1990, and 1149.1-1993, each of which is incorporated herein by reference.
Many IEEE JTAG applications involve a JTAG-specified feature referred to as "Scan Chain Control." Scan Chain Control has a variety of applications and is primarily directed to enhancing internal IC testing via signaling provided at the boundary of the IC. The above-referenced U.S. patent application, Ser. No. 09/283,171 (Docket No. VLSI.228PA) teaches using Scan Chain Control to transfer control from one TAP controller to another TAP controller, without the risk of destroying a current instruction in the instruction register of a TAP controller in communication with the TLM. This is accomplished using the Test Link Module (TLM) to pass a test instruction (e.g., TLM Select instruction) to the TAP controller as part of the step of transferring control.
One particular Scan Chain Control application is directed to ICs having multiple TLM'ed core circuits. In circuit designs of this type, each of multiple cores within the IC includes an internal TLM and multiple TAP controllers with coordination therefor provided by the TLM. A central control agent, such as a chip level TAP Link Module, selectively enables one or more of the TAP controllers in each core. Each of these blocks communicates with the standard JTAG Interface signaling (TDI, TDO, TCK, TMS and TRST). In accordance with aspects of the above-referenced U.S. patent application, Ser. No. 09/283,171 (Docket No. VLSI.228PA), Scan Chain Control can be used to permit access to the Internal TLM modules by the TAP controllers. Depending upon the command loaded into the internal TLM register, the TLM module enables or disables various TAPs in a system by controlling TMS.
Transferring control as described above, however, is problematic for ICs having multiple TLM'ed core circuits. As the level of circuit integration grows, TLMed cores are expected to evolve with more signal processing and control features, just as embedded cores of today have evolved. For design reuse in such futuristic implementations, effectively accommodating such a design evolution would typically involve hierarchical expansion of TLM'ed cores with the hierarchy providing communication among the additional cores. One prior art approach addresses this issue by directly building hierarchical features directly into the TAP controllers. This, however, has required changes to the existing IEEE JTAG 1149.1 specification. This limits potential for core reuse and is therefore disadvantageous.